This application claims the priority benefit of Taiwan application serial no. 90130497, filed Dec. 10, 2001.
1. Field of Invention
The present invention relates to a method for fabricating a non-volatile memory (NVM). More particularly, the present invention relates to a method for fabricating a NROM.
2. Description of Related Art
The family of non-volatile memory includes the electrically erasable and programmable read-only memory (EEPROM), which can be programmed and erased electrically with low power consumption and is capable of retaining data as the power is turned off, and therefore is widely used in personal computers and electronic apparatuses. Particularly, the flash memory among the EEPROM family is highly integrated and has a higher speed for data erasing because the data in a flash memory is erased block by block.
A conventional flash memory comprises a floating gate and a control gate, which two are formed from doped polysilicon. When the flash memory is being programmed, hot electrons are injected into the polysilicon floating gate and are distributed evenly in the entire floating gate. However, when there are defects in the tunnel oxide layer under the polysilicon floating gate, the electrons stored in the floating gate easily leak out so that the reliability of the memory device is lowered.
In order to prevent the leakage and other problems of the EEPROM, a NROM structure is recently provided. When the memory device is programmed with proper biases applied on the control gate and the source/drain region, hot electrons are generated in the channel near the drain region and injected into the charge trapping layer. Since the silicon nitride is capable of trapping electrons, the injected electrons will be localized in the charge trapping layer, rather than distribute evenly in the entire charge trapping layer. Consequently, the charge trapping region is quite small and is thus less likely to locate on the defects of the tunnel oxide layer. The leakage is thereby less in the memory device.
Refer to FIGS. 1Axcx9c1E, which illustrate a process flow of fabricating a NROM in a cross-sectional view in the prior art.
Refer to FIG. 1A, a bottom anti-reflective coating (BARC) 110 is formed on an ONO stacked structure 108 on a substrate 100, wherein the ONO stacked structure 108 comprises a silicon oxide layer 102, a silicon nitride layer 104, and a silicon oxide layer 106. A photoresist pattern 112 is then formed on the bottom anti-reflective coating 110 not covering a region of the substrate 100 in which a buried drain will be formed.
Refer to FIG. 1B, an etching process is then performed to remove the BARC 110 and the stacked structure 108 not covered by the photoresist pattern 112, so as to expose a portion of the substrate 100.
It is noted in the above-mentioned etching process that the photoresist pattern 112 is not only etched vertically to decrease in its effective thickness, but is also etched laterally to cause a pull-back. Consequently, the edge of the BARC 110 not covered by the photoresist pattern 112 will be etched to form an indentation 111 thereat.
Refer to FIG. 1C, an ion implantation is then conducted to form a buried drain 114 in the exposed substrate 100, wherein the edge portion of the silicon oxide layer 106 is also implanted with dopants 116 because of the indentation 111 at the BARC 110.
Refer to FIG. 1D, the photoresist pattern 112 and the BARC 110 are then removed to expose the silicon oxide layer 106. Since the edge portion of the silicon oxide layer 106 having dopants 116 is easily etched by chemical during the removal of the photoresist pattern 112 and the BARC 110, the effective thickness of the edge portion of the ONO stacked structure 108 is decreased. Thereafter, a buried drain oxide layer 118 is formed on the buried drain 114.
Refer to FIG. 1E, a polysilicon layer 120 is then formed on the substrate 100 to cover the ONO stacked structure 108 and the buried drain oxide layer 118. Finally, the polysilicon layer 120 is patterned to form plural gate structures (not shown) perpendicular to the buried drain 114, thus completing the NROM process.
However, since the effective thickness of the edge portion of the ONO stacked structure is decreased during the removal of the photoresist pattern and the BARC, a voltage breakdown occurs more easily in the substrate under the edge portion of the ONO stacked structure to deteriorate the characteristics of the memory device.
Accordingly, this invention provides a method for fabricating a NROM to prevent a pull-back of the photoresist pattern during the patterning of the ONO stacked structure.
This invention also provides a method for fabricating a NROM to maintain the thickness of the edge of the ONO stacked structure, so as to prevent the voltage breakdown of the NROM device.
This invention further provides a method for fabricating a NROM to promote the reliability of the NROM device.
In the method for fabricating a NROM of this invention, a substrate is provided with a charge trapping layer, such as an ONO stacked structure, formed on it. A bottom anti-reflective coating (BARC) and a photoresist pattern are sequentially formed on the charge trapping layer, wherein the photoresist pattern does not cover a region of the substrate in which a buried drain will be formed. An etching process is then performed to pattern the BARC and the charge trapping layer with the photoresist pattern as a mask. The etching process is conducted in an etching chamber equipped with a source power supply and a bias power supply, which two have a power ratio of 1.5xcx9c3, while an etchant used therein is a gas plasma containing trifluoromethane (CHF3) and tetrafluoromethane (CF4). Thereafter, an ion implantation is performed to form a buried drain in the exposed substrate. The photoresist pattern and the BARC are removed and then a buried drain oxide layer is formed on the buried drain. A conductive layer is formed on the substrate to cover the charge trapping layer and the buried drain oxide layer and then patterned to form plural gate structures perpendicular to the buried drain.
Since the etching recipe used in this invention is capable of preventing a pull-back of the photoresist pattern, the edge of the charge trapping layer will not be doped during the ion implantation for forming the buried drain.
Moreover, since the edge portion of the charge trapping layer is not doped during the ion implantation for forming the buried drain, it will not be easily etched by chemical during the removal of the photoresist pattern and the BARC and its thickness will not be decreased.
Because the effective thickness of the edge portion of the charge trapping layer can be maintained, voltage breakdown does not easily occurs in the substrate under the edge portion and the reliability of the device is promoted.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.